1. Field of the Invention
Embodiments of the present invention relate to a phase change memory using a phase change material and a method of fabricating the phase change memory.
2. Description of the Related Art
Currently, various types of three-dimensional (3D) memory devices have been proposed to overcome limitations in two-dimensional (2D) scaling of a NAND flash memory. A 3D NAND flash memory may be provided in, for example, a built-in current sensor (BICS) structure and a bit cost scalable (BiCS) NAND flash cell structure of a piped type that is enhanced from the BICS structure.
A 3D NAND flash memory in the BICS structure uses an oxide-nitride-oxide (ONO) layer as storage and a structure using a trap of a nitride layer may degrade the reliability. Accordingly, research on enhancing the reliability has been continuously conducted.
Also, a 3D NAND flash memory structurally uses an ONO structure as a storage site within a vertical poly silicon channel on a scaling phase. Accordingly, a contact size for a vertical channel is determined based on a thickness of an ONO layer and at least 50 nm needs to be secured when the thickness of the ONO layer is to be 10 nm to 20 nm.
Currently, research on securing a characteristic of a NAND flash structure by applying a resistive memory device, for example, phase change RAM (PRAM) or resistive RAM (ReRAM) to the above 3D structure is ongoing. The resistive memory device may easily configure a cross-point compared to an ONO layer and may also easily perform scaling compared to the ONO layer when configuring a vertical channel or a gate. However, the 3D structure using a resistive change material, for example, PRAM or ReRAM, needs to be enhanced in order to secure the enhanced reliability.
In the existing 3D structure, vertical scaling is difficult and it is difficult to maintain a size of a contact hole of a vertical channel or a gate electrode to be less than or equal to 40 nm due to limitations on a storage thickness. Accordingly, multiple layers including 100 layers or more are required to achieve the same level of integration as a 2D 1×nm class.
In a 3D flash memory structure using a general phase change material, a phase change material may contact with a horizontally formed conductive layer by vertically forming the phase change material on a sidewall of a contact hole. However, due to resistance of the conductive layer, it is difficult to decrease the contact size to be less than or equal to 20 nm. In addition, a memory phase change material and a heater layer are formed within the contact hole and thus, scaling is difficult compared to a structure using an ONO layer.
A general 3D flash memory uses an ONO storage film in a vertical direction within a contact hole. In this structure, charge storage areas are not separated between cells and thus, inter-cell interference may increase, which may lead to making it difficult to apply a multi-level cell (MLC). Also, in the general 3D flash memory structure, a resistive change layer is vertically formed within the contact hole and is connected to a horizontally formed conductive layer. Accordingly, the resistance change layer is not separated between cells and a single resistance change layer is used and thus, the reliability may be degraded in view of a technical aspect for MLC.